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A 5-stage instruction pipeline with equal stage delays executes 100 instructions with no stalls. Compared with a non-pipelined processor th…

1990Medium DSSSB TGT Computer Science 0 replies

A 5-stage instruction pipeline with equal stage delays executes 100 instructions with no stalls. Compared with a non-pipelined processor that takes 5 stage-times per instruction, the speedup is approximately

A4.76
B5.00
C4.81
D5.05

Correct answer: C

Explanation

Pipelined time = (5 + 99) = 104 stage-times against 100 x 5 = 500, so speedup = 500 / 104 = 4.81.

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